參數(shù)資料
型號(hào): PIC16C432T-E/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 54/70頁(yè)
文件大小: 0K
描述: IC MCU CMOS 8BIT 20MHZ 2K 20SSOP
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 12
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
配用: AC164029-ND - MODULE SKT PROMATEII 20DIP/SSOP
PIC16C432
DS41140B-page 56
Preliminary
2002 Microchip Technology Inc.
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run even
if the clock on the OSC1 and OSC2 pins of the device
have been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 9.1).
9.7.1
WDT PERIOD
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control, by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
9.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT timeout occurs.
FIGURE 9-17:
WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-8:
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
BOREN
CP1
CP0
PWRTE
WDTE
FOSC1
FOSC0
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: _ = Unimplemented location, read as “0”, + = Reserved for future use
Note 1: Shaded cells are not used by the Watchdog Timer.
From TMR0 Clock Source
To TMR0 (Figure 6-6)
Postscaler
Watchdog
Timer
M
U
X
PSA
8 - to -1 MUX
PSA
WDT
Timeout
1
0
1
WDT
Enable Bit
PS<2:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
8
MUX
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