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參數(shù)資料
型號(hào): PIC16C433-I/SO
廠商: Microchip Technology
文件頁數(shù): 35/126頁
文件大?。?/td> 0K
描述: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
PIC16C433
DS41139B-page 14
Preliminary
2002 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRIS
GPIO Data Direction Register
--11 1111
86h
Unimplemented
87h
Unimplemented
88h
Unimplemented
89h
Unimplemented
8Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
8Ch
PIE1
—ADIE
-0-- ----
8Dh
Unimplemented
8Eh
PCON
—POR
---- --0-
---- --u-
8Fh
OSCCAL
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
0111 00--
uuuu uu--
90h
Unimplemented
91h
Unimplemented
92h
Unimplemented
93h
Unimplemented
94h
Unimplemented
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
98h
Unimplemented
99h
Unimplemented
9Ah
Unimplemented
9Bh
Unimplemented
9Ch
Unimplemented
9Dh
Unimplemented
9Eh
Unimplemented
9Fh
ADCON1
PCFG2
PCFG1
PCFG0
---- -000
TABLE 4-1:
PIC16C433 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS(3)
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred
to the upper byte of the program counter.
3:
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C433; always maintain these bits clear.
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