參數(shù)資料
型號: PIC16C433T-E/SO
廠商: Microchip Technology
文件頁數(shù): 79/126頁
文件大小: 0K
描述: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
標準包裝: 1,100
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
56
4378C–AVR–09/08
AT90PWM1
0xC01
out
SPH,r16
; Set Stack Pointer to top of RAM
0xC02
ldi
r16,low(RAMEND)
0xC03
out
SPL,r16
0xC04
sei
; Enable interrupts
0xC05
<instr>
xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses in AT90PWM1 is:
Address
Labels Code
Comments
;
.org 0xC00
0xC00
rjmp
RESET
; Reset handler
0xC01
rjmp
PSC2_CAPT
; PSC2 Capture event Handler
0xC02
rjmp
PSC2_EC
; PSC2 End Cycle Handler
...
;
0xC1F
rjmp
SPM_RDY
; Store Program Memory Ready Handler
;
0xC20
RESET: ldi
r16,high(RAMEND); Main program start
0xC21
out
SPH,r16
; Set Stack Pointer to top of RAM
0xC22
ldi
r16,low(RAMEND)
0xC23
out
SPL,r16
0xC24
sei
; Enable interrupts
0xC25
<instr>
xxx
10.1.1
Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
10.1.2
MCU Control Register – MCUCR
Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-
mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 205 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1.
Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
Bit
765
43210
SPIPS
PUD
IVSEL
IVCE
MCUCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
000
00000
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