參數(shù)資料
型號: PIC16C620A-04/P
廠商: Microchip Technology
文件頁數(shù): 45/89頁
文件大小: 0K
描述: IC MCU OTP 512X14 COMP 18DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 896B(512 x 14)
程序存儲器類型: OTP
RAM 容量: 96 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 635 (CN2011-ZH PDF)
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
5
AT90S1200
0838H–AVR–03/02
Architectural
Overview
The fast-access register file concept contains 32 x 8-bit general purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file – in one clock cycle.
Figure 4. The AT90S1200 AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept – with separate memories and buses for program and data
memories. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
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