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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16C622-20/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/89闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 2KX14 COMP 18DIP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 25 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 13 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 3 V ~ 6 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 18-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE AC164010-ND - MODULE SKT PROMATEII DIP/SOIC |
| 鍏跺畠鍚嶇ū锛� | PIC16C622-20/PR PIC16C622-20/PR-ND |
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18
AT90S1200
0838H鈥揂VR鈥�03/02
MCU Control Register 鈥�
MCUCR
The MCU Control Register contains general microcontroller control bits for general MCU
control functions.
Bits 7, 6 鈥� Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
Bit 5 鈥� SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-
grammers purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
Bit 4 鈥� SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to the paragraph 鈥淪leep Modes鈥� on the following page.
Bits 3, 2 鈥� Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
Bits 1, 0 鈥� ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK register is set. The level and edges on the
external INT0 pin that activate the interrupt are defined in Table 4.
The value on the INT0 pin is sampled before detecting edges. If edge interrupt is
selected, pulses with a duration longer than one CPU clock period will generate an inter-
rupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Bit
765
432
10
$35
鈥撯€�
SE
SM
鈥撯€�
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R
R/W
Initial Value
0
Table 4. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
01
Reserved
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
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