參數(shù)資料
型號: PIC16C622T-20I/SO
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18
封裝: 0.300 INCH, PLASTIC, MS-013, SO-18
文件頁數(shù): 70/128頁
文件大?。?/td> 3677K
代理商: PIC16C622T-20I/SO
PIC16C62X
DS30235J-page 44
2003 Microchip Technology Inc.
EXAMPLE 8-1:
VOLTAGE REFERENCE
CONFIGURATION
8.2
Voltage Reference Accuracy/Error
The full range of V
SS to VDD cannot be realized due to the
construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 8-1)
keep V
REF from approaching VSS or VDD. The voltage
reference is V
DD derived and therefore, the VREF output
changes with fluctuations in V
DD. The tested absolute
accuracy of the voltage reference can be found in
8.3
Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
8.4
Effects of a RESET
A device RESET disables the voltage reference by
clearing bit V
REN (VRCON<7>). This reset also
disconnects the reference from the RA2 pin by clearing
bit V
ROE (VRCON<6>) and selects the high voltage
range by clearing bit V
RR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
8.5
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit is set and the V
ROE bit, VRCON<6>, is
set. Enabling the voltage reference output onto the
RA2 pin with an input signal present will increase
current consumption. Connecting RA2 as a digital
output with V
REF enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
voltage reference output for external connections to
V
REF.
shows
an
example
buffering
technique.
FIGURE 8-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 8-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Note:
- = Unimplemented, read as "0"
MOVLW
0x02
; 4 Inputs Muxed
MOVWF
CMCON
; to 2 comps.
BSF
STATUS,RP0
; go to Bank 1
MOVLW
0x0F
; RA3-RA0 are
MOVWF
TRISA
; inputs
MOVLW
0xA6
; enable VREF
MOVWF
VRCON
; low range
; set VR<3:0>=6
BCF
STATUS,RP0
; go to Bank 0
CALL
DELAY10
; 10
s delay
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
RESETS
9Fh
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
1Fh
CMCON
C2OUT
C1OUT
CIS
CM2
CM1
CM0
00-- 0000
85h
TRISA
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
V
REF Output
+
V
REF
Module
Voltage
Reference
Output
Impedance
R(1)
RA
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
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