參數(shù)資料
型號: PIC16C62B-04/SS
廠商: Microchip Technology
文件頁數(shù): 62/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 PWM 28SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 47
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: AC164307-ND - MODULE SKT FOR PM3 28SSOP
309-1025-ND - ADAPTER 28-SSOP TO 28-DIP
PIC16C62B/72A
DS35008B-page 46
Preliminary
1999 Microchip Technology Inc.
REGISTER 8-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
SMP: SPI data input sample phase
SPI Master Operation
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
I2C Mode
This bit must be maintained clear
bit 6:
CKE: SPI Clock Edge Select
SPI Mode
CKP = 0
1
= Data transmitted on rising edge of SCK
0
= Data transmitted on falling edge of SCK
CKP = 1
1
= Data transmitted on falling edge of SCK
0
= Data transmitted on rising edge of SCK
I2C Mode
This bit must be maintained clear
bit 5:
D/A: Data/Address bit (I2C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last, SSPEN is cleared)
1
= Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0
= Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1
= Indicates that a start bit has been detected last (this bit is '0' on RESET)
0
= Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1
= Read
0
= Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1
= Transmit in progress, SSPBUF is full
0
= Transmit complete, SSPBUF is empty
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