參數(shù)資料
型號: PIC16C62B-20I/ML
廠商: Microchip Technology
文件頁數(shù): 81/120頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 PWM 28QFN
標準包裝: 61
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
其它名稱: PIC16C62B20I/ML
PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 63
10.10.1 INT INTERRUPT
The external interrupt on RB0/INT pin is edge trig-
gered: either rising, if bit INTEDG (OPTION_REG<6>)
is set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 10.13 for details on SLEEP mode.
10.10.2 TMR0 INTERRUPT
An overflow (FFh
→ 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
10.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
10.11
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 10-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0, it must also be defined at 0xA0 in bank
1).
The example:
a)
Stores the W register.
b)
Stores the STATUS register in bank 0.
c)
Stores the PCLATH register.
d)
Executes the interrupt service routine code
(User-generated).
e)
Restores the STATUS register (and bank select
bit).
f)
Restores the W and PCLATH registers.
EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
W_TEMP
;Copy W to TEMP register, could be bank one or zero
SWAPF
STATUS,W
;Swap status to be saved into W
CLRF
STATUS
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF
STATUS_TEMP
;Save status to bank zero STATUS_TEMP register
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF
STATUS
;Move W into STATUS register
SWAPF
W_TEMP,F
;Swap W_TEMP
SWAPF
W_TEMP,W
;Swap W_TEMP into W
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