參數(shù)資料
型號(hào)： PIC16C63-20/SP
廠商： Microchip Technology
文件頁數(shù)： 58/126頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 PWM 28DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
配用： DVMCPA-ND - KIT DVR BOARD EVAL SYSTEM MXDEV1
1997 Microchip Technology Inc.
DS30234D-page 37
PIC16C6X
4.2.2.3
INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains the various enable and ag bits for
the TMR0 register overow, RB port change and exter-
nal RB0/INT pin interrupts.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
Interrupt ag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-11: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh 18Bh)
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
x
= unknown
bit7
bit0
bit 7:
GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE:(2) Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overow Interrupt Enable bit
1 = Enables the TMR0 overow interrupt
0 = Disables the TMR0 overow interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overow Interrupt Flag bit
1 = TMR0 register overowed (must be cleared in software)
0 = TMR0 register did not overow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear the interrupt)
0 = None of the RB7:RB4 pins have changed state
Note 1:
For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally
be re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 13.5 for a detailed
description.
2:
The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'.
Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ag bits are clear prior to
enabling an interrupt.
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