參數資料
型號： PIC16C642T-20I/SO
廠商： Microchip Technology
文件頁數： 57/125頁
文件大小： 0K
描述： IC MCU OTP 4KX14 COMP 28SOIC
標準包裝： 1,600
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： 欠壓檢測/復位，LED，POR，WDT
輸入/輸出數： 22
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 176 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
37
M9999-040407-3.0
D[7:0]
D[15:8]
D[23:16]
D[31:24]
GND
HD[7:0]
nHBE[0]
nHBE[2]
nHBE[3]
HD[15:8]
nHBE[1]
HD[23:16]
HD[31:24]
A[15:2]
A[1]
D[7:0]
D[15:8]
BE0N
BE1N
8-bit Data Bus
HA[1]
HA[15:2]
HD[7:0]
HA[0]
VDD
A[15:2]
A[1]
D[7:0]
D[15:8]
BE0N
BE1N
16-bit Data Bus
(for example: ISA-like)
HA[1]
HA[15:2]
HD[7:0]
HA[0]
nSBHE
A[15:2]
A[1]
BE0N
BE1N
BE2N
BE3N
32-bit Data Bus
(for example: EISA-like)
HA[15:2]
HD[15:8]
KSZ8862-16
KSZ8862-32
Figure 10. KSZ8862M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections
BIU Implementation Principles
Since the KSZ8862M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4
and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is
assumed (BE3N – BE0N are ignored).
If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN=0.
1.
Byte, word, and double-word data buses and accesses (transfers) are supported.
2.
Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 12 for the
appropriate 8-bit, 16-bit, and 32-bit data bus connection.
3.
Since independent sets of synchronous and asynchronous signals are provided, synchronous and asynchronous
cycles can be mixed or interleaved as long as they are not active simultaneously.
4.
The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de-
asserted on the leading edge of the strobe.
5.
The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write
operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must
be held until RDYRTNN is asserted.
6.
The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal
VLBUSN = 1. Both the system/host/memory and KSZ8862M are capable of inserting wait states. To set the
system/host/memory to insert a wait state, assert RDYRTNN signal. To set the KSZ8862M to insert a wait state,
assert SRDYN signal.
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