參數(shù)資料
型號: PIC16C64A-04I/P
廠商: Microchip Technology
文件頁數(shù): 40/126頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 PWM 40DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
配用: 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
PIC16C6X
DS30234D-page 20
1997 Microchip Technology Inc.
FIGURE 4-4:
PIC16C66/67 PROGRAM
MEMORY MAP AND STACK
4.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00
→ Bank0
= 01
→ Bank1
= 10
→ Bank2
= 11
→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
4.2.1
GENERAL PURPOSE REGISTERS
These registers are accessed either directly or indi-
rectly
through
the
File
Select
Register
(FSR)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PC<12:0>
Stack Level 1
Stack Level 8
User
Memor
y
Space
CALL, RETURN
RETFIE, RETLW
13
0000h
0004h
0FFFh
1000h
On-chip Program
Memory (Page 0)
On-chip Program
Memory (Page 1)
0005h
Reset Vector
Peripheral Interrupt Vector
07FFh
0800h
On-chip Program
Memory (Page 2)
On-chip Program
Memory (Page 3)
17FFh
1800h
1FFFh
For the PIC16C61, general purpose register locations
8Ch-AFh of Bank 1 are not physically implemented.
These locations are mapped into 0Ch-2Fh of Bank 0.
FIGURE 4-5:
PIC16C61 REGISTER FILE
MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
2Fh
30h
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
AFh
B0h
FFh
Bank 0
Bank 1
INDF(1)
TMR0
OPTION
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
General
Purpose
Register
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
Mapped
in Bank 0(2)
Unimplemented data memory location; read as '0'.
Note 1:
Not a physical register.
2:
These locations are unimplemented in
Bank 1. Any access to these locations will
access the corresponding Bank 0 register.
File Address
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