參數(shù)資料
型號(hào): PIC16C64A-20I/L
廠商: Microchip Technology
文件頁數(shù): 51/126頁
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 PWM 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP
309-1039-ND - ADAPTER 44-PLCC TO 40-DIP
其它名稱: PIC16C64A-20I/LR
PIC16C64A-20I/LR-ND
PIC16C6X
DS30234D-page 30
1997 Microchip Technology Inc.
TABLE 4-5:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
03h(1)
STATUS
IRP(5)
RP1(5)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
04h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
PORTA Data Latch when written: PORTA pins when read
--xx xxxx
--uu uuuu
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx
uuuu uuuu
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx
uuuu uuuu
09h
PORTE
RE2
RE1
RE0
---- -xxx
---- -uuu
0Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF
(6)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0Dh
PIR2
—–
CCP2IF
---- ---0
0Eh
TMR1L
Holding register for the Least Signicant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Signicant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
11h
TMR2
Timer2 module’s register
0000 0000
12h
T2CON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
FERR
OERR
RX9D
0000 -00x
19h
TXREG
USART Transmit Data Register
0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000
1Bh
CCPR2L
Capture/Compare/PWM2 (LSB)
xxxx xxxx
uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM2 (MSB)
xxxx xxxx
uuuu uuuu
1Dh
CCP2CON
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
1Eh-1Fh
Unimplemented
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5:
The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6:
PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
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