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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16C64AT-10/L
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 54/126闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU OTP 2KX14 PWM 44PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 500
绯诲垪锛� PIC® 16C
鏍稿績铏曠悊鍣細 PIC
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 33
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 OTP
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
鍖呰锛� 甯跺嵎 (TR)
閰嶇敤锛� 309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP
309-1039-ND - ADAPTER 44-PLCC TO 40-DIP
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1997 Microchip Technology Inc.
DS30234D-page 33
PIC16C6X
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111
89h(5)
TRISE
IBF
OBF
IBOV
PSPMODE
鈥�
PORTE Data Direction Bits
0000 -111
8Ah(1,2)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
PSPIE(6)
(4)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
鈥�
CCP2IE
---- ---0
8Eh
PCON
鈥�
POR
BOR
---- --qq
---- --uu
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
鈥�
Unimplemented
鈥�
TABLE 4-6:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.鈥檇)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
These registers can be addressed from any bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5:
PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6:
PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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