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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC16C67-20E/L
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 55/126闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 27
绯诲垪锛� PIC® 16C
鏍稿績铏曠悊鍣細 PIC
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RAM 瀹归噺锛� 368 x 8
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鎸暕鍣ㄥ瀷锛� 澶栭儴
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灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
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PIC16C6X
DS30234D-page 34
1997 Microchip Technology Inc.
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
101h
TMR0
Timer0 module鈥檚 register
xxxx xxxx
uuuu uuuu
102h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
103h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
104h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
105h
鈥�
Unimplemented
鈥�
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
107h
鈥�
Unimplemented
鈥�
108h
鈥�
Unimplemented
鈥�
109h
鈥�
Unimplemented
鈥�
10Ah(1,2) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
10Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Ch-
10Fh
鈥�
Unimplemented
鈥�
Bank 3
180h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
183h(1)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
184h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah(1,2) PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
18Ch-
19Fh
鈥�
Unimplemented
鈥�
TABLE 4-6:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.鈥檇)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
These registers can be addressed from any bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5:
PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6:
PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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