參數(shù)資料
型號： PIC16C710-20I/SS
廠商： Microchip Technology
文件頁數(shù)： 85/177頁
文件大小： 0K
描述： IC MCU OTP 512X14 A/D 20SSOP
產品培訓模塊： Asynchronous Stimulus
標準包裝： 67
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： 欠壓檢測/復位，POR，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 896B（512 x 14）
程序存儲器類型： OTP
RAM 容量： 36 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉換器： A/D 4x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
包裝： 管件
配用： 309-1016-ND - ADAPTER 20-SSOP TO 18-DIP
175
7593L–AVR–09/12
AT90USB64/128
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
Bit 5..1 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Bit 0 – SPI2X: Double SPI Speed bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 18-4 on page 174). This means that the minimum SCK period will
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to
work at f
osc/4 or lower.
The SPI interface on the AT90USB64/128 is also used for program memory and EEPROM
downloading or uploading. See page 373 for serial programming and verification.
18.1.5
SPDR – SPI Data Register
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
18.2
Data modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
18-3 on page 176 and Figure 18-4 on page 176. Data bits are shifted out and latched in on
opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 18-2 on page 174 and Table 18-3 on page 174, as done
below:
Bit
7
6
5
43
21
0
MSB
LSB
SPDR
Read/write
R/W
Initial value
X
Undefined
Table 18-5.
CPOL functionality.
Leading edge
Trailing edge
SPI mode
CPOL=0, CPHA=0
Sample (rising)
Setup (falling)
0
CPOL=0, CPHA=1
Setup (rising)
Sample (falling)
1
CPOL=1, CPHA=0
Sample (falling)
Setup (rising)
2
CPOL=1, CPHA=1
Setup (falling)
Sample (rising)
3
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