參數(shù)資料
型號: PIC16C711-04/SS
廠商: Microchip Technology
文件頁數(shù): 15/177頁
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D 20SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 67
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: OTP
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 管件
配用: XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
AC164307-ND - MODULE SKT FOR PM3 28SSOP
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1016-ND - ADAPTER 20-SSOP TO 18-DIP
111
7593L–AVR–09/12
AT90USB64/128
Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 14-7. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 103).
Notes:
1. MAX
= 0xFF
2. BOTTOM = 0x00
14.8.2
TCCR0B – Timer/Counter Control Register B
Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
Table 14-7.
Waveform Generation Mode bit description.
Mode
WGM2
WGM1
WGM0
Timer/Counter mode of
operation
TOP
Update of
OCRx at
TOV flag
set on
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, phase correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
Fast PWM
0xFF
TOP
MAX
4
1
0
Reserved
5
1
0
1
PWM, phase correct
OCRA
TOP
BOTTOM
6
1
0
Reserved
7
1
Fast PWM
OCRA
TOP
Bit
7
6
543
2
1
0
FOC0A
FOC0B
WGM02
CS02
CS01
CS00
TCCR0B
Read/write
W
R
R/W
Initial value
0
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