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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16C72-04E/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 36/114闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 2KX14 A/D PWM 28SSOP |
| 妯欐簴鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�鐣跺墠绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�
PIC16C7X
DS30390E-page 28
1997 Microchip Technology Inc.
Bank 1
80h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(4)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(4)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(4)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111
89h(5)
TRISE
IBF
OBF
IBOV
PSPMODE
鈥�
PORTE Data Direction Bits
0000 -111
8Ah(1,4)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
鈥�
CCP2IE
---- ---0
8Eh
PCON
鈥�
POR
BOR
---- --qq
---- --uu
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1
鈥�
PCFG2
PCFG1
PCFG0
---- -000
TABLE 4-3:
PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.鈥檇)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD and PORTE are not physically implemented on the PIC16C76, read as 鈥�0鈥�.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| PIC16C72-04E/SP | IC MCU OTP 2KX14 A/D PWM 28DIP |
| PIC16C72-04E/SO | IC MCU OTP 2KX14 A/D PWM 28SOIC |
| PIC16C71T-20/SO | IC MCU OTP 1KX14 A/D 18SOIC |
| PIC16C71T-20I/SO | IC MCU OTP 1KX14 A/D 18SOIC |
| VE-B1D-IV-S | CONVERTER MOD DC/DC 85V 150W |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC16C72-04I/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72-04I/SP | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72-04I/SS | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72-04SP | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪: |
| PIC16C72-10/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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