參數(shù)資料
型號(hào): PIC16C73
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontroller with A/D Converter(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流,1路捕捉/比較/PWM的微控制器)
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器(每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流,1路捕捉/比較/脈寬調(diào)制的微控制器)
文件頁(yè)數(shù): 103/308頁(yè)
文件大?。?/td> 2351K
代理商: PIC16C73
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1995 Microchip Technology Inc.
DS30390B-page 103
PIC16C7X
12.3
USART Synchronous Master Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
In Master Synchronous mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting bit SYNC
(TXSTA<4>). In addition enable bit SPEN (RCSTA<7>)
is set in order to configure the RC6/TX/CK and
RC7/RX/DT I/O pins to CK (clock) and DT (data) lines
respectively. The Master mode indicates that the pro-
cessor transmits the master clock on the CK line. The
Master mode is entered by setting bit CSRC
(TXSTA<7>).
12.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and an
interrupt bit, TXIF (PIR1<4>) is set. The interrupt can
be enabled or disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register.
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory
so it is not available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-11). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN. This is advantageous when slow baud rates are
selected, since the BRG is kept in reset when bits
TXEN, CREN, and SREN are clear. Setting enable bit
TXEN will start the BRG, creating a shift clock immedi-
ately. Normally when transmission is first started, the
TSR register is empty, so a transfer to the TXREG reg-
ister will result in an immediate transfer to TSR result-
ing in an empty TXREG. Back-to-back transfers are
possible.
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN are set, during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from hi-impedance
receive mode to transmit and start driving. To avoid
this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting bit TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the
TXREG register.
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