參數(shù)資料
型號: PIC16C73A-20I/SP
廠商: Microchip Technology
文件頁數(shù): 18/114頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 A/D PWM 28DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
PIC16C7X
DS30390E-page 114
1997 Microchip Technology Inc.
12.4
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
12.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP
instruction is executed, the following will occur:
a)
The rst word will immediately transfer to the
TSR register and transmit.
b)
The second word will remain in TXREG register.
c)
Flag bit TXIF will not be set.
d)
When the rst word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and ag bit TXIF will now be
set.
e)
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, then set enable bit
TXIE.
4.
If 9-bit transmission is desired, then set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the
TXREG register.
Applicable Devices
72 73 73A 74 74A 76 77
12.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP
instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2.
If interrupts are desired, then set enable bit
RCIE.
3.
If 9-bit reception is desired, then set bit RX9.
4.
To enable reception, set enable bit CREN.
5.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7.
Read the 8-bit received data by reading the
RCREG register.
8.
If any error occurred, clear the error by clearing
bit CREN.
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