PIC16C7X
DS30390E-page 280
1997 Microchip Technology Inc.
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 4-1:
PIC16C72 Block Diagram .........................10
PIC16C73/73A/76 Block Diagram.............11
PIC16C74/74A/77 Block Diagram.............12
Clock/Instruction Cycle..............................17
PIC16C72 Program Memory Map
and Stack ..................................................19
PIC16C73/73A/74/74A Program
Memory Map and Stack ............................19
PIC16C76/77 Program Memory
Map and Stack ..........................................20
PIC16C72 Register File Map ....................21
PIC16C73/73A/74/74A Register
File Map ....................................................21
PIC16C76/77 Register File Map ...............22
Status Register (Address 03h,
83h, 103h, 183h)......................................30
OPTION Register (Address 81h,
181h).........................................................31
INTCON Register
(Address 0Bh, 8Bh, 10bh, 18bh)...............32
PIE1 Register PIC16C72
(Address 8Ch)...........................................33
PIE1 Register PIC16C73/73A/
74/74A/76/77 (Address 8Ch).....................34
PIR1 Register PIC16C72
(Address 0Ch)...........................................35
PIR1 Register PIC16C73/73A/
74/74A/76/77 (Address 0Ch).....................36
PIE2 Register (Address 8Dh)....................37
PIR2 Register (Address 0Dh)....................38
PCON Register (Address 8Eh) .................39
Loading of PC In Different
Situations ..................................................40
Direct/Indirect Addressing.........................41
Block Diagram of RA3:RA0
and RA5 Pins ............................................43
Block Diagram of RA4/T0CKI Pin .............43
Block Diagram of RB3:RB0 Pins...............45
Block Diagram of RB7:RB4 Pins
(PIC16C73/74) ..........................................46
Block Diagram of
RB7:RB4 Pins (PIC16C72/73A/
74A/76/77).................................................46
PORTC Block Diagram
(Peripheral Output Override)....................48
PORTD Block Diagram
(in I/O Port Mode).....................................50
PORTE Block Diagram
(in I/O Port Mode).....................................51
TRISE Register (Address 89h)..................51
Successive I/O Operation .........................53
PORTD and PORTE Block Diagram
(Parallel Slave Port) ..................................54
Parallel Slave Port Write Waveforms........55
Parallel Slave Port Read Waveforms........55
Timer0 Block Diagram...............................59
Timer0 Timing: Internal Clock/No
Prescale ....................................................59
Timer0 Timing: Internal
Clock/Prescale 1:2 ....................................60
Timer0 Interrupt Timing.............................60
Timer0 Timing with External Clock............61
Block Diagram of the Timer0/WDT
Prescaler...................................................62
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Figure 4-12:
Figure 4-13:
Figure 4-14:
Figure 4-15:
Figure 4-16:
Figure 4-17:
Figure 4-18:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Figure 5-11:
Figure 5-12:
Figure 5-13:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 8-1:
T1CON: Timer1 Control Register
(Address 10h) .......................................... 65
Timer1 Block Diagram .............................. 66
Timer2 Block Diagram .............................. 69
T2CON: Timer2 Control Register
(Address 12h) .......................................... 70
CCP1CON Register (Address 17h)/
CCP2CON Register (Address 1Dh).......... 72
Capture Mode Operation
Block Diagram .......................................... 72
Compare Mode Operation
Block Diagram .......................................... 73
Simplified PWM Block Diagram................ 74
PWM Output ............................................. 74
SSPSTAT: Sync Serial Port Status
Register (Address 94h)............................. 78
SSPCON: Sync Serial Port Control
Register (Address 14h)............................. 79
SSP Block Diagram (SPI Mode)............... 80
SPI Master/Slave Connection................... 81
SPI Mode Timing, Master Mode
or Slave Mode w/o SS Control.................. 82
SPI Mode Timing, Slave Mode with
SS Control ................................................ 82
SSPSTAT: Sync Serial Port Status
Register (Address 94h)(PIC16C76/77)..... 83
SSPCON: Sync Serial Port Control
Register (Address 14h)(PIC16C76/77)..... 84
SSP Block Diagram (SPI Mode)
(PIC16C76/77).......................................... 85
SPI Master/Slave Connection
PIC16C76/77)........................................... 86
SPI Mode Timing, Master Mode
(PIC16C76/77)......................................... 87
SPI Mode Timing (Slave Mode
With CKE = 0) (PIC16C76/77)................. 87
SPI Mode Timing (Slave Mode
With CKE = 1) (PIC16C76/77).................. 88
Start and Stop Conditions......................... 89
7-bit Address Format ................................ 90
I
2
C 10-bit Address Format........................ 90
Slave-receiver Acknowledge .................... 90
Data Transfer Wait State .......................... 90
Master-transmitter Sequence ................... 91
Master-receiver Sequence........................ 91
Combined Format..................................... 91
Multi-master Arbitration
(Two Masters)........................................... 92
Clock Synchronization .............................. 92
SSP Block Diagram
(I
2
C Mode) ................................................ 93
I
2
C Waveforms for Reception
(7-bit Address) .......................................... 95
I
2
C Waveforms for Transmission
(7-bit Address) .......................................... 96
Operation of the I
2
C Module in
IDLE_MODE, RCV_MODE or
XMIT_MODE ............................................ 98
TXSTA: Transmit Status and
Control Register (Address 98h) ................ 99
RCSTA: Receive Status and
Control Register (Address 18h) .............. 100
RX Pin Sampling Scheme. BRGH = 0
(PIC16C73/73A/74/74A)......................... 104
RX Pin Sampling Scheme, BRGH = 1
(PIC16C73/73A/74/74A)......................... 104
Figure 8-2:
Figure 9-1:
Figure 9-2:
Figure 10-1:
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Figure 10-5:
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Figure 11-27:
Figure 12-1:
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Figure 12-3:
Figure 12-4: