參數(shù)資料
型號: PIC16C745-I/SO
廠商: Microchip Technology
文件頁數(shù): 130/165頁
文件大?。?/td> 0K
描述: IC MCU OTP 8KX14 USB A/D 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 24MHz
連通性: SCI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.35 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 67
PIC16C745/765
10.5.1.9
Endpoint Registers
Each endpoint is controlled by an Endpoint Control
Register.
The
PIC16C745/765
supports
Buffer
Descriptors (BD) for the following endpoints:
- EP0 Out
- EP0 In
- EP1 Out
- EP1 In
- EP2 Out
- EP2 In
The user will be required to disable unused Endpoints
and directions using the Endpoint Control Registers.
10.5.1.10 USB Endpoint Control Register (EPCn)
The Endpoint Control Register contains the endpoint
control bits for each of the 6 endpoints available on
USB for a decoded address. These four bits define the
control necessary for any one endpoint. Endpoint 0
(ENDP0) is associated with control pipe 0 which is
required by USB for all functions (IN, OUT, and
SETUP). Therefore, after a USB_RST interrupt has
been received, the microprocessor should set UEP0 to
contain 06h.
REGISTER 10-9:
USB ENDPOINT CONTROL REGISTER (UEPn: 198H-19Ah)
Note:
These registers are initialized in response
to a RESET from the host. The user
must
modify
function
USBReset
in
USB_CH9.ASM to configure the endpoints
as needed for the application.
U-0
R/W-0
EP_CTL_DIS
EP_OUT_EN EP_IN_EN EP_STALL
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7
bit0
bit 7-4:
Unimplemented: Read as ’0’
bit 3-1:
EP_CTL_DIS, EP_OUT_EN, EP_IN_EN: These three bits define if an endpoint is enabled and the direc-
tion of the endpoint. The endpoint enable/direction control is defined as follows:
bit 0:
EP_STALL: When this bit is set it indicates that the endpoint is stalled. This bit has priority over all other
control bits in the Endpoint Enable register, but is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access
to this endpoint will cause the USB to return a STALL handshake. The EP_STALL bit can be set or cleared
by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL
protocol.
EP_CTL_DIS EP_OUT_EN
EP_IN_EN
Endpoint Enable/Direction Control
X
0
Disable Endpoint
X
0
1
Enable Endpoint for IN tokens only
X
1
0
Enable Endpoint for OUT tokens only
1
Enable Endpoint for IN and OUT tokens
0
1
Enable Endpoint for IN, OUT, and SETUP tokens
745cov.book Page 67 Wednesday, August 2, 2000 8:24 AM
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