
1995 Microchip Technology Inc.
DS30390B-page 75
PIC16C7X
TABLE 10-5:
REGISTERS ASSOCIATED WITH CAPTURE AND TIMER1
TABLE 10-6:
REGISTERS ASSOCIATED WITH COMPARE AND TIMER1
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
BOR
Value on all
other resets
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF
(1,2)
ADIF
RCIF
(2)
TXIF
(2)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
0Dh
(2)
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
8Ch
PIE1
PSPIE
(1,2)
ADIE
RCIE
(2)
TXIE
(2)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
8Dh
(2)
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000
--uu uuuu
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0
--00 0000
--00 0000
1Bh
(2)
CCPR2L
Capture/Compare/PWM register2 (LSB)
xxxx xxxx
uuuu uuuu
1Ch
(2)
CCPR2H
Capture/Compare/PWM register2 (MSB)
xxxx xxxx
uuuu uuuu
1Dh
(2)
CCP2CON
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2 CCP2M1 CCP2M0
--00 0000
--00 0000
Legend:
Note 1:
x
Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
= unknown,
u
= unchanged,
-
= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
2:
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
BOR
Value on all
other resets
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF
(1,2)
ADIF
RCIF
(2)
TXIF
(2)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
0Dh
(2)
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
8Ch
PIE1
PSPIE
(1,2)
ADIE
RCIE
(2)
TXIE
(2)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
8Dh
(2)
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000
--uu uuuu
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0
--00 0000
--00 0000
1Bh
1Ch
(2)
1Dh
(2)
(2)
CCPR2L
Capture/Compare/PWM register2 (LSB)
xxxx xxxx
uuuu uuuu
CCPR2H
Capture/Compare/PWM register2 (MSB)
xxxx xxxx
uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2 CCP2M1 CCP2M0
--00 0000
--00 0000
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented read as '0'. Shaded cells are not used by Compare and Timer1.
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2:
The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.