參數(shù)資料
型號(hào)： PIC16C74A-04/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 11/114頁(yè)
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D PWM 40DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 10
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
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PIC16C7X
DS30390E-page 108
1997 Microchip Technology Inc.
12.2.2
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 12-10.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, ag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
by
setting/clearing
enable
bit
RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, i.e. it is a two deep FIFO. It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte begin shift-
ing to the RSR register. On the detection of the STOP
bit of the third byte, if the RCREG register is still full
then overrun error bit OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM
FIGURE 12-11: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR register
MSb
LSb
RX9D
RCREG register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop
Start
(8)
7
1
0
RX9
Start
bit
bit7/8
bit1
bit0
bit7/8
bit0
Stop
bit
Start
bit
Start
bit
bit7/8
Stop
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt ag)
OERR bit
CREN
WORD 1
RCREG
WORD 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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