參數(shù)資料
型號: PIC16C74A-20/L
廠商: Microchip Technology
文件頁數(shù): 92/114頁
文件大小: 0K
描述: IC MCU OTP 4KX14 A/D PWM 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
1997 Microchip Technology Inc.
DS30390E-page 79
PIC16C7X
FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overow Detect bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overow,
the data in SSPSR register is lost. Overow can only occur in slave mode. The user must read the SSP-
BUF, even if only transmitting data, to avoid setting overow. In master mode the overow bit is not set
since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and congures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and congures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and congures the SDA and SCL pins as serial port pins
0 = Disables serial port and congures these pins as I/O port pins
In both modes, when enabled, these pins must be properly congured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.
0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000
= SPI master mode, clock = Fosc/4
0001
= SPI master mode, clock = Fosc/16
0010
= SPI master mode, clock = Fosc/64
0011
= SPI master mode, clock = TMR2 output/2
0100
= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101
= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110
= I2C slave mode, 7-bit address
0111
= I2C slave mode, 10-bit address
1011
= I2C firmware controlled Master Mode (slave idle)
1110
= I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111
= I2C slave mode, 10-bit address with start and stop bit interrupts enabled
Applicable Devices
72 73 73A 74 74A 76 77
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