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鍨嬭櫉锛� PIC16C74BT-04/L
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 90/184闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU OTP 4KX14 A/D PWM 44PLCC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 500
绯诲垪锛� PIC® 16C
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 33
绋嬪簭瀛樺劜鍣ㄥ閲忥細 7KB锛�4K x 14锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 OTP
RAM 瀹归噺锛� 192 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
鍖呰锛� 甯跺嵎 (TR)
閰嶇敤锛� 309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP
309-1039-ND - ADAPTER 44-PLCC TO 40-DIP
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PIC16C63A/65B/73B/74B
DS30605C-page 18
2000 Microchip Technology Inc.
Bank 1
80h
INDF(4)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
82h
PCL(4)
Program Counter鈥檚 (PC) Least Significant Byte
0000 0000 0000 0000
83h
STATUS(4)
IRP(2)
RP1(2)
RP0
TO
PD
ZDC
C
0001 1xxx 000q quuu
84h
FSR(4)
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
85h
TRISA
鈥�
PORTA Data Direction Register
--11 1111 --11 1111
86h
TRISB
PORTB Data Direction register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction register
1111 1111 1111 1111
88h
TRISD(5)
PORTD Data Direction register
1111 1111 1111 1111
89h
TRISE(5)
IBF
OBF
IBOV
PSPMODE
鈥�
PORTE Data Direction bits
0000 -111 0000 -111
8Ah
PCLATH(1,4)
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh
INTCON(4)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(5)
ADIE(6)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
鈥�
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
鈥�
POR
BOR
---- --qq ---- --uu
8Fh
鈥�
Unimplemented
鈥�
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
PR2
Timer2 Period register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address register
0000 0000 0000 0000
94h
SSPSTAT
鈥�
D/A
PS
R/W
UA
BF
--00 0000 --00 0000
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010 0000 -010
99h
SPBRG
Baud Rate Generator register
0000 0000 0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1(6)
鈥�
PCFG2
PCFG1
PCFG0
---- -000
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 鈥�0鈥�.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>.
2: The IRP and RP1 bits are reserved; always maintain these bits clear.
3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
4: These registers can be addressed from either bank.
5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and
registers clear.
6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.
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