參數(shù)資料
型號: PIC16C765-I/L
廠商: Microchip Technology
文件頁數(shù): 14/165頁
文件大小: 0K
描述: IC MCU OTP 8KX14 USB 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 24MHz
連通性: SCI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.35 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
PIC16C745/765
DS41124C-page 110
Preliminary
2000 Microchip Technology Inc.
13.8
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip dedi-
cated oscillator, which does not require any external
components. The WDT will run, even if the clock on the
OSC1/CLKIN and OSC2/CLKOUT pins of the device
has been stopped, for example, by execution of a
SLEEP
instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEP instruction prevents the WDT from generat-
ing a RESET, but will allow the WDT to wake the device
from SLEEP mode.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 13-8:
SUMMARY OF WATCHDOG TIMER REGISTERS
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
2007h
Config. bits
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
PLL
FOSC0
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1:
See Register 13-1 for operation of these bits.
From TMR0 Clock Source
To TMR0 MUX
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS<2:0>
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION register.
8
745cov.book Page 110 Wednesday, August 2, 2000 8:24 AM
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