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| 型號： | PIC16C782T-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 39/186頁 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 2K 20MHZ 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b; D/A 1x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164028-ND - MODULE SKT PROMATEII 20SOIC/DIP |
| 其它名稱： | PIC16C782TI/SO |
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2001 Microchip Technology Inc.
Preliminary
DS41171A-page 131
PIC16C781/782
14.12 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer is cleared but keeps
running, the PD bit (STATUS<3>) is cleared, the TO
(STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode:
place all I/O pins at either VDD, or VSS,
ensure no external circuitry is drawing current
from the I/O pin,
power-down all peripherals,
disable external clocks.
Pull all I/O pins that are hi-impedance inputs, high or low
externally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS for
lowest current consumption. The contribution from on-
chip pull-ups on PORTB should be considered.
14.12.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
External RESET input on MCLR pin.
2.
Watchdog
Timer
Wake-up
(if
WDT
was
enabled).
3.
Interrupt from INT pin, PORTB IOCB, or any
Peripheral Interrupts.
External MCLR Reset causes a device RESET. All other
events are considered a continuation of program execu-
tion and cause a "wake-up". The TO and PD bits in the
STATUS register can be used to determine the cause of
device RESET. The PD bit, which is set on power-up, is
cleared when SLEEP is invoked. The TO bit is cleared if
a WDT time-out occurred (and caused wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2.
ADC conversion (when ADC clock source is RC).
3.
Programmable low voltage detect.
4.
Comparator C1 or C2 interrupt-on-change.
5.
OPA in Comparator mode using IOCB.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
14.12.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs before the execution of a
SLEEP
instruction, the SLEEP instruction com-
pletes as a NOP. Therefore, the WDT and WDT
postscaler are not cleared, the TO bit is not set,
and PD bits are not cleared.
If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device immedi-
ately awakens from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler are cleared, the TO bit is set, and the
PD bit is cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
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