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| 型號(hào)： | PIC16C923 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Bit CMOS Microcontroller with LCD Driver(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流，1路捕捉/比較/PWM的微控制器) |
| 中文描述： | 8位CMOS微控制器與LCD驅(qū)動(dòng)器（每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流，1路捕捉/比較/脈寬調(diào)制的微控制器） |
| 文件頁(yè)數(shù)： | 72/189頁(yè) |
| 文件大?。?/td> | 1544K |
| 代理商： | PIC16C923 |
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PIC16C9XX
DS30444E - page 72
1997 Microchip Technology Inc.
11.2.4
MULTI-MASTER
The I
2
C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbi-
tration and synchronization occur.
11.2.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when the
other master transmits a low loses arbitration
(Figure 11-16), and turns off its data output stage. A
master which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 11-16: MULTI-MASTER
ARBITRATION
(TWO MASTERS)
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning mas-
ter-transmitter may be addressing it.
Arbitration is not allowed between:
A repeated START condition
A STOP condition and a data bit
A repeated START condition and a STOP condi-
tion
Care needs to be taken to ensure that these conditions
do not occur.
transmitter 1 loses arbitration
DATA 1 SDA
DATA 1
DATA 2
SDA
SCL
11.2.4.2 Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high tran-
sition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait-state, until the SCL line comes high. When the
SCL line comes high, all devices start counting off their
high periods. The first device to complete its high period
will pull the SCL line low. The SCL line high time is
determined by the device with the shortest high period,
Figure 11-17.
FIGURE 11-17: CLOCK SYNCHRONIZATION
CLK
1
CLK
2
SCL
wait
state
start counting
HIGH period
counter
reset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16C923-04/L | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C923-04/L | 制造商:Microchip Technology Inc 功能描述:8BIT CMOS MCU SMD 16C923 PLCC68 |
| PIC16C923-04/PT | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C923-04/SP | 制造商:Microchip Technology Inc 功能描述: |
| PIC16C923-04I/L | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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