參數(shù)資料
型號： PIC16CR74
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 21/172頁
文件大?。?/td> 1506K
代理商： PIC16CR74
2007 Microchip Technology Inc.
DS21993C-page 19
PIC16CR7X
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the Reset status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example,
CLRF STATUS
will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as
‘000u u1uu’
(where
u
= unchanged).
It is recommended, therefore, that only
BCF, BSF,
SWAPF
and
MOVWF
instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any Status bits, see the
“Instruction Set Summary.”
REGISTER 2-1:
Note 1:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the
SUBLW
and
SUBWF
instructions for examples.
STATUS: (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP:
Register Bank Select bit (used for indirect addressing)
1
= Bank 2, 3 (100h-1FFh)
0
= Bank 0, 1 (00h-FFh)
RP1:RP0
: Register Bank Select bits (used for direct addressing)
11
= Bank 3 (180h-1FFh)
10
= Bank 2 (100h-17Fh)
01
= Bank 1 (80h-FFh)
00
= Bank 0 (00h-7Fh)
Each bank is 128 bytes
TO
: Time-out bit
1
= After power-up,
CLRWDT
instruction or
SLEEP
instruction
0
= A WDT time-out occurred
PD
: Power-down bit
1
= After power-up or by the
CLRWDT
instruction
0
= By execution of the
SLEEP
instruction
Z
: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
DC
: Digit carry/borrow bit (
ADDWF
,
ADDLW, SUBLW, SUBWF
instructions)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
C:
Carry/borrow bit (
ADDWF, ADDLW, SUBLW, SUBWF
instructions)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (
RRF, RLF
) instructions, this bit is loaded with either the high or low order bit
of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
相關(guān)PDF資料
PDF描述
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