參數(shù)資料
型號(hào)： PIC16CR76T-I/SS
廠商： Microchip Technology
文件頁數(shù)： 137/172頁
文件大?。?/td> 0K
描述： IC PIC MCU 8KX14 28SSOP
標(biāo)準(zhǔn)包裝： 2,100
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 14KB（8K x 14）
程序存儲(chǔ)器類型： ROM
RAM 容量： 368 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
2007 Microchip Technology Inc.
DS39599G-page 65
PIC18F2220/2320/4220/4320
5.10
Access Bank
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
Intermediate computational values
Local variables of subroutines
Faster context saving/switching of variables
Common variables
Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a(chǎn)’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
5.11
Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR since the 12-bit
addresses are embedded into the instruction word.
Registers” provides a description of indirect address-
ing which allows linear addressing of the entire RAM
space.
FIGURE 5-7:
DIRECT ADDRESSING
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addressing
Bank Select(2)
Location Select(3)
BSR<3:0>
7
0
From Opcode(3)
00h
01h
0Eh
0Fh
Bank 0
Bank 1
Bank 14
Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
BSR<7:4>
00
0
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