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鍙冩暩璩囨枡
鍨嬭櫉锛� PIC16F1825-E/P
寤犲晢锛� Microchip Technology
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鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU PIC 14K FLASH 1K RAM 14DIP
鐢㈠搧鍩硅〒妯″锛� 8-bit PIC® Microcontroller Portfolio
鐗硅壊鐢㈠搧锛� Extreme Low Power (XLP) Microcontrollers
妯欐簴鍖呰锛� 30
绯诲垪锛� PIC® XLP™ mTouch™ 16F
鏍稿績铏曠悊鍣細 PIC
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澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁革細 11
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
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RAM 瀹归噺锛� 1K x 8
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鏁告摎杞夋彌鍣細 A/D 8x10b
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2010-2012 Microchip Technology Inc.
DS41440C-page 33
PIC16(L)F1825/1829
Bank 2
100h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
101h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
102h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
103h(1)
STATUS
鈥�
鈥擳O
PD
ZDC
C
---1 1000 ---q quuu
104h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
105h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
106h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
107h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
108h(1)
BSR
鈥�
BSR<4:0>
---0 0000 ---0 0000
109h(1)
WREG
Working Register
0000 0000 uuuu uuuu
10Ah(1)
PCLATH
鈥�
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 0000 0000 0000
10Ch
LATA
鈥�
鈥擫ATA5
LATA4
鈥�
LATA2
LATA1
LATA0
--xx -xxx --uu -uuu
10Dh
LATB(2)
LATB7
LATB6
LATB5
LATB4
鈥�
xxxx ---- xxxx ----
10Eh
LATC
LATC7(2)
LATC6(2)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx uuuu uuuu
10Fh
鈥�
Unimplemented
鈥�
110h
鈥�
Unimplemented
鈥�
111h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
鈥�
C1SP
C1HYS
C1SYNC 0000 -100 0000 -100
112h
CM1CON1
C1INTP
C1INTN
C1PCH<1:0>
鈥�
C1NCH1
C1NCH0
0000 ---0 0000 ---0
113h
CM2CON0
C2ON
C2OUT
C2OE
C2POL
鈥�
C2SP
C2HYS
C2SYNC 0000 -100 0000 -100
114h
CM2CON1
C2INTP
C2INTN
C2PCH<1:0>
鈥�
C2NCH<1:0>
0000 --00 0000 --00
115h
CMOUT
鈥�
鈥擬C2OUT
MC1OUT ---- --00 ---- --00
116h
BORCON
SBOREN
鈥�
BORRDY 1--- ---q u--- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
118h
DACCON0
DACEN
DACLPS
DACOE
鈥�
DACPSS<1:0>
鈥�
DACNSS 000- 00-0 000- 00-0
119h
DACCON1
鈥�
DACR<4:0>
---0 0000 ---0 0000
11Ah
SRCON0
SRLEN
SRCLK<2:0>
SRQEN
SRNQEN
SRPS
SRPR
0000 0000 0000 0000
11Bh
SRCON1
SRSPE
SRSCKE
SRSC2E(2)
SRSC1E
SRRPE
SRRCKE
SRRC2E(2)
SRRC1E 0000 0000 0000 0000
11Ch
鈥�
Unimplemented
鈥�
11Dh
APFCON0
RXDTSEL SDO1SEL(3)
SS1SEL(3)
鈥�
T1GSEL
TXCKSEL
鈥�
000- 0000 000- 0000
11Eh
APFCON1
鈥�
SDO2SEL(2) SS2SEL(2)
P1DSEL
P1CSEL
P2BSEL
CCP2SEL --00 0000 --00 0000
11Fh
鈥�
Unimplemented
鈥�
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1: These registers can be addressed from any bank.
2: PIC16(L)F1829 only.
3: PIC16(L)F1825 only.
4: Unimplemented, read as 鈥�1鈥�.
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