參數(shù)資料
型號(hào): PIC16F59-E/P
廠商: Microchip Technology
文件頁數(shù): 6/88頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX12 40DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 3KB(2K x 12)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 134 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
PIC16F5X
DS41213D-page 12
2007 Microchip Technology Inc.
2.1
Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1 and
the instruction is fetched from program memory and
latched into the instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
2.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the Program Counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the instruction register in cycle Q1. This instruction
is then decoded and executed during the Q2, Q3 and
Q4 cycles. Data memory is read during Q2 (operand
read) and written during Q4 (destination write).
FIGURE 2-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 2-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC + 1
PC + 2
Fetch INST (PC)
Execute INST (PC - 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW H'55'
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. CALL
SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, BIT3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
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