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| 型號(hào)： | PIC16F627A-I/SS |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 158/180頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 1KX14 EEPROM 20SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 67 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器容量： | 1.75KB（1K x 14） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 224 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 638 (CN2011-ZH PDF) |
| 配用： | XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP I3DBF648-ND - BOARD DAUGHTER ICEPIC3 AC164307-ND - MODULE SKT FOR PM3 28SSOP AC162053-ND - HEADER INTERFACE ICD,ICD2 18DIP |
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2009 Microchip Technology Inc.
DS40044G-page 79
PIC16F627A/628A/648A
12.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8-bit. A dedicated 8-bit baud rate generator is used to
derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The baud rate generator produces a clock either
x16 or x64 of the bit shift rate, depending on bit BRGH
(TXSTA<2>). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
12.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register (occurs
in one TCY), the TXREG register is empty and flag bit
TXIF (PIR1<4>) is set. This interrupt can be enabled/
disabled
by
setting/clearing
enable
bit
TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicated the
status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register.
Status bit TRMT is a read-only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 12-1). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate
transfer to TSR resulting in an empty TXREG. A back-
to-back transfer is thus possible (Figure 12-3). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will reset the
transmitter. As a result the RB2/TX/CK pin will revert to
high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
Note 1:
The TSR register is not mapped in data
memory so it is not available to the user.
2:
Flag bit TXIF is set when enable bit TXEN
is set.
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| PIC16F627AT-E/SO | 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ext Temp SOIC18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F627AT-E/SS | 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ext Temp SSOP20 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F627AT-I/ML | 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ind Temp QFN28 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F627AT-I/SO | 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ind Temp SOIC18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F627AT-I/SS | 功能描述:8位微控制器 -MCU 1.75KB 224 RAM 16I/O Ind Temp SSOP20 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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