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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F676-I/ML
寤犲晢锛� Microchip Technology
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8-bit PIC® Microcontroller Portfolio
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2010 Microchip Technology Inc.
DS40039F-page 77
PIC16F630/676
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) - 1
(destination);
skip if result = 0
Status Affected:
None
Description:
The contents of register 鈥榝鈥� are
decremented. If 鈥榙鈥� is 0, the result
is placed in the W register. If 鈥榙鈥� is
1, the result is placed back in
register 鈥榝鈥�.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOP is executed instead,
making it a 2-cycle instruction.
GOTO
Unconditional Branch
Syntax:
[ label ] GOTO k
Operands:
0
k 2047
Operation:
k
PC<10:0>
PCLATH<4:3>
PC<12:11>
Status Affected:
None
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF
Increment f
Syntax:
[ label ] INCF f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination)
Status Affected:
Z
Description:
The contents of register 鈥榝鈥� are
incremented. If 鈥榙鈥� is 0, the result
is placed in the W register. If 鈥榙鈥� is
1, the result is placed back in
register 鈥榝鈥�.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) + 1
(destination),
skip if result = 0
Status Affected:
None
Description:
The contents of register 鈥榝鈥� are
incremented. If 鈥榙鈥� is 0, the result
is placed in the W register. If 鈥榙鈥� is
1, the result is placed back in
register 鈥榝鈥�.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOP is executed instead, making
it a 2-cycle instruction.
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] IORLW k
Operands:
0
k 255
Operation:
(W) .OR. k
(W)
Status Affected:
Z
Description:
The contents of the W register are
OR鈥檈d with the eight-bit literal 鈥榢鈥�.
The result is placed in the W
register.
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORWF f,d
Operands:
0
f 127
d
[0,1]
Operation:
(W) .OR. (f)
(destination)
Status Affected:
Z
Description:
Inclusive OR the W register with
register 鈥榝鈥�. If 鈥榙鈥� is 0, the result is
placed in the W register. If 鈥榙鈥� is 1,
the result is placed back in
register 鈥榝鈥�.
鐩搁棞(gu膩n)PDF璩囨枡
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