參數(shù)資料
型號： PIC16F676T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 48/132頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 1KX14 16QFN
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 3,300
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復位，POR，WDT
輸入/輸出數(shù)： 12
程序存儲器容量： 1.75KB（1K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-VQFN 裸露焊盤
包裝： 帶卷 (TR)
配用： AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
PIC16F630/676
DS40039F-page 22
2010 Microchip Technology Inc.
REGISTER 3-2:
TRISA — PORTA TRI-STATE REGISTER (ADDRESS: 85h)
REGISTER 3-3:
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
3.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTA. This will end the
mismatch condition.
b) Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
U-0
R/W-x
R-1
R/W-x
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as ‘0’
bit 5-0:
TRISA<5:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note:
TRISA<3> always reads 1.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
U-0
R/W-1
U-0
R/W-1
—
WPUA5
WPUA4
—
WPUA2
WPUA1
WPUA0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
WPUA<5:4>: Weak Pull-up Register bits
1
= Pull-up enabled
0
= Pull-up disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WPUA<2:0>: Weak Pull-up Register bits
1
= Pull-up enabled
0
= Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
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