參數(shù)資料
型號: PIC16F716-E/ML
廠商: Microchip Technology
文件頁數(shù): 13/136頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 2KX14 28QFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 61
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
配用: I3-DB16F716-ND - BOARD DAUGHTER ICEPIC3
2007 Microchip Technology Inc.
DS41206B-page 9
PIC16F716
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY BANK 0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
00h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
02h
PCL(1)
Program Counter’s (PC) Least Significant Byte
0000 0000
03h
STATUS(1)
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
04h
FSR(1)
Indirect Data Memory Address Pointer
xxxx xxxx
05h
PORTA(5,6)
(7)
RA4
RA3
RA2
RA1
RA0
---x 0000
06h
PORTB(5,6)
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
07h-09h
Unimplemented
0Ah
PCLATH(1,2)
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh
INTCON(1)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0Ch
PIR1
—ADIF
CCP1IF
TMR2IF
TMR1IF
-0-- -000
0Dh
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
10h
T1CON
T1CKPS1
T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
11h
TMR2
Timer2 Module’s Register
0000 0000
12h
T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
13h-14h
Unimplemented
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
17h
CCP1CON
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
18h
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
19h
ECCPAS
ECCPASE ECCPAS2
(8)
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
00-0 0000
1Ah-1Dh
Unimplemented
1Eh
ADRES
A/D Result Register
xxxx xxxx
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
(7)
ADON
0000 0000
Legend:
x
= unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Note
1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3:
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved. Always maintain these bits clear.
5:
On any device Reset, these pins are configured as inputs.
6:
This is the value that will be in the PORT output latch.
7:
Reserved bits, do not use.
8:
ECCPAS1 bit is not used on PIC16F716.
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