參數(shù)資料
型號: PIC16F84-04/P
廠商: Microchip Technology
文件頁數(shù): 6/80頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 EE 18DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
配用: DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
PIC16F8X
DS30430C-page 14
1998 Microchip Technology Inc.
TABLE 4-1
REGISTER FILE SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h
PCL
Low order 8 bits of the Program Counter (PC)
0000 0000
03h
STATUS
(2)
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
04h
FSR
Indirect data memory address pointer 0
xxxx xxxx
uuuu uuuu
05h
PORTA
RA4/T0CKI
RA3
RA2
RA1
RA0
---x xxxx
---u uuuu
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
xxxx xxxx
uuuu uuuu
07h
Unimplemented location, read as '0'
---- ----
08h
EEDATA
EEPROM data register
xxxx xxxx
uuuu uuuu
09h
EEADR
EEPROM address register
xxxx xxxx
uuuu uuuu
0Ah
PCLATH
Write buffer for upper 5 bits of the PC
(1)
---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Bank 1
80h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ----
81h
OPTION_
REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h
PCL
Low order 8 bits of Program Counter (PC)
0000 0000
83h
STATUS
(2)
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h
FSR
Indirect data memory address pointer 0
xxxx xxxx
uuuu uuuu
85h
TRISA
PORTA data direction register
---1 1111
86h
TRISB
PORTB data direction register
1111 1111
87h
Unimplemented location, read as '0'
---- ----
88h
EECON1
EEIF
WRERR
WREN
WR
RD
---0 x000
---0 q000
89h
EECON2
EEPROM control register 2 (not a physical register)
---- ----
0Ah
PCLATH
Write buffer for upper 5 bits of the PC
(1)
---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Legend: x = unknown, u = unchanged. - = unimplemented read as ’0’, q = value depends on condition.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred
to PCLATH.
2:
The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
3:
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
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