參數(shù)資料
型號(hào)： PIC16F84-10I/P
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 43/80頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 1KX14 EE 18DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 25
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 68 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 18-DIP（0.300"，7.62mm）
包裝： 管件
配用： DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
48
M9999-083109-2.0
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3
This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.
Bit
Default Value
R/W
Description
15-0
0
RW
WF3BM3
Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes 49 to 64 of a
Wake up frame 3 pattern.
0x6C – 0x6F: Reserved
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit
Default Value
R/W
Description
15-9
-
RO
Reserved
8
0x0
RW
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851SNL is enabled to transmit ICMP frame (only for non-
fragment frame) checksum generation.
7
0x0
RO
Reserved
6
0x0
RW
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851SNL is enabled to transmit TCP frame checksum
generation.
5
0x0
RW
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851SNL is enabled to transmit IP header checksum
generation.
4
0x0
RW
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit to
normal operation.
3
0x0
RW
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851SNL is in full-duplex mode, flow control is enabled.
The KSZ8851SNL transmits a PAUSE frame when the Receive Buffer capacity reaches a
threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851SNL is in half-duplex mode, back-pressure flow
control is enabled. When this bit is cleared, no transmit flow control is enabled.
2
0x0
RW
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851SNL automatically adds a padding field to a packet
shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC errors
for the transmit packet.
1
0x0
RW
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851SNL automatically adds a 32-bit CRC checksum field to
the end of a transmit frame.
0
0x0
RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current frame is completed.
Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
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