參數(shù)資料
型號: PIC16F84A-20I/P
廠商: Microchip Technology
文件頁數(shù): 35/81頁
文件大小: 0K
描述: IC MCU FLASH 1KX14 EE 18DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 25
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大小: 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
配用: I3-DB16F84A-ND - BOARD DAUGHTER ICEPIC3
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
PIC16F84A
DS35007B-page 38
2000 Microchip Technology Inc.
BTFSC
Bit Test, Skip if Clear
Syntax:
[
label] BTFSC f,b
Operands:
0
≤ f ≤ 127
0
≤ b ≤ 7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’ in register ’f’ is ’0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2TCY instruction.
CALL
Call Subroutine
Syntax:
[
label ] CALL k
Operands:
0
≤ k ≤ 2047
Operation:
(PC)+ 1
→ TOS,
k
→ PC<10:0>,
(PCLATH<4:3>)
→ PC<12:11>
Status Affected:
None
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
CLRF
Clear f
Syntax:
[
label] CLRF
f
Operands:
0
≤ f ≤ 127
Operation:
00h
→ (f)
1
→ Z
Status Affected:
Z
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[
label ] CLRW
Operands:
None
Operation:
00h
→ (W)
1
→ Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
CLRWDT
Clear Watchdog Timer
Syntax:
[
label ] CLRWDT
Operands:
None
Operation:
00h
→ WDT
0
→ WDT prescaler,
1
→ TO
1
→ PD
Status Affected:
TO, PD
Description:
CLRWDT
instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
COMF
Complement f
Syntax:
[
label ] COMF
f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
(f)
→ (destination)
Status Affected:
Z
Description:
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
DECF
Decrement f
Syntax:
[
label] DECF f,d
Operands:
0
≤ f ≤ 127
d
∈ [0,1]
Operation:
(f) - 1
→ (destination)
Status Affected:
Z
Description:
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
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