
PIC16F882/883/884/886/887
DS41291D-page 280
Preliminary
2007 Microchip Technology Inc.
STATUS......................................................................29
T1CON........................................................................79
T2CON........................................................................82
TRISA (Tri-State PORTA)...........................................39
TRISB (Tri-State PORTB)...........................................48
TRISC (Tri-State PORTC) ..........................................53
TRISD (Tri-State PORTD) ..........................................57
TRISE (Tri-State PORTE)...........................................59
TXSTA (Transmit Status and Control) ......................158
VRCON (Voltage Reference Control) .........................97
WDTCON (Watchdog Timer Control)........................221
WPUB (Weak Pull-up PORTB)...................................49
Reset.................................................................................208
Revision History................................................................273
S
SCK...................................................................................179
SDI....................................................................................179
SDO ..................................................................................179
Serial Clock, SCK..............................................................179
Serial Data In, SDI ............................................................179
Serial Data Out, SDO........................................................179
Serial Peripheral Interface.
See
SPI
Shoot-through Current ......................................................143
Slave Mode General Call Address Sequence...................188
Slave Select Synchronization............................................182
Slave Select, SS ...............................................................179
Sleep.................................................................................222
Wake-up....................................................................222
Wake-up Using Interrupts .........................................222
Software Simulator (MPLAB SIM).....................................236
SPBRG..............................................................................161
SPBRGH...........................................................................161
Special Event Trigger........................................................102
Special Function Registers .................................................22
SPI
Master Mode.............................................................181
Serial Clock...............................................................179
Serial Data In ............................................................179
Serial Data Out .........................................................179
Slave Select..............................................................179
SPI clock...................................................................181
SPI Mode ..................................................................179
SPI Bus Modes .................................................................184
SPI Mode
Associated Registers with SPI Operation .................184
Bus Mode Compatibility ............................................184
Effects of a Reset......................................................184
Enabling SPI I/O .......................................................180
Operation ..................................................................179
Sleep Operation........................................................184
SPI Module
Slave Mode...............................................................182
Slave Select Synchronization ...................................182
Slave Synchronization Timing...................................182
Slave Timing with CKE = 0 .......................................183
Slave Timing with CKE = 1 .......................................183
SRCON Register.................................................................93
SS .....................................................................................179
SSP
SSPBUF....................................................................181
SSPSR......................................................................181
SSPCON Register.............................................................177
SSPCON2 Register...........................................................178
SSPMSK Register.............................................................204
SSPOV..............................................................................194
SSPOV Status Flag .......................................................... 194
SSPSTAT Register........................................................... 176
R/W Bit ..................................................................... 186
STATUS Register............................................................... 29
T
T1CON Register................................................................. 79
T2CON Register................................................................. 82
Thermal Considerations.................................................... 247
Time-out Sequence .......................................................... 211
Timer0................................................................................. 73
Associated Registers.................................................. 75
External Clock............................................................. 74
Interrupt ...................................................................... 75
Operation.............................................................. 73, 76
Specifications ........................................................... 254
T0CKI ......................................................................... 74
Timer1................................................................................. 76
Associated Registers.................................................. 80
Asynchronous Counter Mode..................................... 77
Reading and Writing........................................... 77
Interrupt ...................................................................... 78
Modes of Operation.................................................... 76
Operation During Sleep.............................................. 78
Oscillator..................................................................... 77
Prescaler .................................................................... 77
Specifications ........................................................... 254
Timer1 Gate
Inverting Gate..................................................... 77
Selecting Source .......................................... 77, 91
SR Latch............................................................. 92
Synchronizing COUT w/Timer1.......................... 91
TMR1H Register......................................................... 76
TMR1L Register.......................................................... 76
Timer2
Associated Registers.................................................. 82
Timers
Timer1
T1CON ............................................................... 79
Timer2
T2CON ............................................................... 82
Timing Diagrams
A/D Conversion......................................................... 259
A/D Conversion (Sleep Mode).................................. 259
Acknowledge Sequence Timing ............................... 197
Asynchronous Reception.......................................... 156
Asynchronous Transmission..................................... 152
Asynchronous Transmission (Back to Back)............ 152
Auto Wake-up Bit (WUE) During Normal Operation. 166
Auto Wake-up Bit (WUE) During Sleep.................... 167
Automatic Baud Rate Calibration.............................. 165
Baud Rate Generator with Clock Arbitration............. 191
BRG Reset Due to SDA Arbitration.......................... 201
Brown-out Reset (BOR)............................................ 252
Brown-out Reset Situations...................................... 210
Bus Collision
Start Condition Timing...................................... 200
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 202
Bus Collision During a Repeated Start Condition
(Case2)............................................................. 202
Bus Collision During a Start Condition (SCL = 0)..... 201
Bus Collision During a Stop Condition...................... 203
Bus Collision for Transmit and Acknowledge ........... 199
CLKOUT and I/O ...................................................... 251
Clock Timing............................................................. 249