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    參數(shù)資料
    型號: PIC16LC505-04I/P
    廠商: Microchip Technology
    文件頁數(shù): 16/90頁
    文件大小: 0K
    描述: IC MCU OTP 1KX12 14DIP
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    標準包裝: 30
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設(shè)備: POR,WDT
    輸入/輸出數(shù): 12
    程序存儲器容量: 1.5KB(1K x 12)
    程序存儲器類型: OTP
    RAM 容量: 72 x 8
    電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 14-DIP(0.300",7.62mm)
    包裝: 管件
    1999-2012 Microchip Technology Inc.
    DS40192D-page 23
    PIC16C505
    6.0
    TIMER0 MODULE AND TMR0
    REGISTER
    The Timer0 module has the following features:
    8-bit timer/counter register, TMR0
    - Readable and writable
    8-bit software programmable prescaler
    Internal or external clock select
    - Edge select for external clock
    Figure 6-1 is a simplified block diagram of the Timer0
    module.
    Timer mode is selected by clearing the T0CS bit
    (OPTION<5>). In timer mode, the Timer0 module will
    increment every instruction cycle (without prescaler). If
    TMR0 register is written, the increment is inhibited for
    the following two cycles (Figure 6-2 and Figure 6-3).
    The user can work around this by writing an adjusted
    value to the TMR0 register.
    Counter mode is selected by setting the T0CS bit
    (OPTION<5>). In this mode, Timer0 will increment
    either on every rising or falling edge of pin T0CKI. The
    T0SE bit (OPTION<4>) determines the source edge.
    Clearing the T0SE bit selects the rising edge.
    Restrictions on the external clock input are discussed
    in detail in Section 6.1.
    The prescaler may be used by either the Timer0
    module or the Watchdog Timer, but not both. The
    prescaler assignment is controlled in software by the
    control bit PSA (OPTION<3>). Clearing the PSA bit
    will assign the prescaler to Timer0. The prescaler is
    not readable or writable. When the prescaler is
    assigned to the Timer0 module, prescale values of 1:2,
    1:4,..., 1:256 are selectable. Section 6.2 details the
    operation of the prescaler.
    A summary of registers associated with the Timer0
    module is found in Table 6-1.
    FIGURE 6-1:
    TIMER0 BLOCK DIAGRAM
    Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
    2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
    0
    1
    0
    T0CS(1)
    FOSC/4
    Programmable
    Prescaler(2)
    Sync with
    Internal
    Clocks
    TMR0 reg
    PSout
    (2 TCY delay)
    PSout
    Data Bus
    8
    PSA(1)
    PS2, PS1, PS0(1)
    3
    Sync
    T0SE
    RC5/T0CKI
    Pin
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