參數(shù)資料
      型號(hào): PIC16LC554-04/SO
      廠商: Microchip Technology
      文件頁(yè)數(shù): 27/108頁(yè)
      文件大小: 0K
      描述: IC MCU OTP 512X14 18SOIC
      產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
      標(biāo)準(zhǔn)包裝: 42
      系列: PIC® 16C
      核心處理器: PIC
      芯體尺寸: 8-位
      速度: 4MHz
      外圍設(shè)備: POR,WDT
      輸入/輸出數(shù): 13
      程序存儲(chǔ)器容量: 896B(512 x 14)
      程序存儲(chǔ)器類型: OTP
      RAM 容量: 80 x 8
      電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
      振蕩器型: 外部
      工作溫度: 0°C ~ 70°C
      封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
      包裝: 管件
      2002 Microchip Technology Inc.
      Preliminary
      DS40143D-page 23
      PIC16C55X
      5.0
      I/O PORTS
      The PIC16C554 and PIC16C558 have two ports,
      PORTA and PORTB. The PIC16C557 has three ports,
      PORTA, PORTB and PORTC.
      5.1
      PORTA and TRISA Registers
      PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
      input and an open-drain output. Port RA4 is multiplexed
      with the T0CKI clock input. All other RA port pins have
      Schmitt Trigger input levels and full CMOS output driv-
      ers. All pins have data direction bits (TRIS registers)
      which can configure these pins as input or output.
      A '1' in the TRISA register puts the corresponding out-
      put driver in a Hi-impedance mode. A '0' in the TRISA
      register puts the contents of the output latch on the
      selected pin(s).
      Reading the PORTA register reads the status of the
      pins, whereas writing to it will write to the port latch. All
      write operations are read-modify-write operations. So a
      write to a port implies that the port pins are first read,
      then this value is modified and written to the port data
      latch.
      FIGURE 5-1:
      BLOCK DIAGRAM OF
      PORT PINS RA<3:0>
      FIGURE 5-2:
      BLOCK DIAGRAM OF RA4
      PIN
      Note 1: On RESET, the TRISA register is set to all
      inputs.
      Data
      Bus
      Q
      D
      Q
      CK
      Q
      D
      Q
      CK
      QD
      EN
      P
      N
      WR
      PORTA
      WR
      TRISA
      Data Latch
      TRIS Latch
      RD TRISA
      RD PORTA
      Schmitt
      input
      buffer
      V
      SS
      V
      DD
      I/O pin
      Trigger
      V
      SS
      V
      DD
      Data
      bus
      WR
      PORTA
      WR
      TRISA
      RD PORTA
      Data Latch
      TRISA Latch
      RD TRISA
      Schmitt
      Trigger
      input
      buffer
      N
      V
      SS
      I/O pin(1)
      TMR0 clock input
      Q
      D
      Q
      CK
      Q
      D
      Q
      CK
      EN
      QD
      EN
      V
      SS
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