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    參數(shù)資料
    型號(hào): PIC16LC662T-04I/PQ
    廠商: Microchip Technology
    文件頁數(shù): 84/125頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 4KX14 COMP 44-MQFP
    標(biāo)準(zhǔn)包裝: 900
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,WDT
    輸入/輸出數(shù): 33
    程序存儲(chǔ)器容量: 7KB(4K x 14)
    程序存儲(chǔ)器類型: OTP
    RAM 容量: 176 x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 6 V
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-QFP
    包裝: 帶卷 (TR)
    其它名稱: PIC16LC662T-04IPQ
    Micrel, Inc.
    KSZ8862-16/32MQL
    April 2007
    61
    M9999-040407-3.0
    Bank 3 Bus Configuration Register (0x08): BCFG
    This register is a read-only register. The bit 0 is automatically downloaded from bit 0 Configparm word of EEPROM, if pin
    EEEN is high (enabled EEPROM)
    Bit
    Default Value
    R/W
    Description
    15-1
    0x0000
    RO
    Reserved
    0
    -
    RO
    Bus Configuration (only for KSZ8862-16 device)
    1: bus width is 16 bits.
    0: bus width is 8 bits.
    (this bit is only avaiable when EEPROM is enabled)
    Banks 4 – 15: Reserved
    Except Bank Select Register (0xE).
    Bank 16 Transmit Control Register (0x00): TXCR
    This register holds control information programmed by the CPU to control the QMU transmit module function.
    Bit
    Default Value
    R/W
    Description
    15
    -
    RO
    Reserved
    14
    0x0
    RW
    Reserved
    13
    0x0
    RW
    Reserved
    12-4
    -
    RO
    Reserved
    3
    0x0
    RW
    TXFCE Transmit Flow Control Enable
    When this bit is set, the QMU sends flow control pause frames from the host port if the RX
    FIFO has reached its threshold.
    Note: the SGCR3[5] in Bank 32 also needs to be enabled.
    2
    0x0
    RW
    TXPE Transmit Padding Enable
    When this bit is set, the KSZ8862M automatically adds a padding field to a packet shorter
    than 64 bytes.
    Note: Setting this bit requires enabling the ADD CRC feature to avoid CRC errors for the
    transmit packet.
    1
    0x0
    RW
    TXCE Transmit CRC Enable
    When this bit is set, the KSZ8862M automatically adds a CRC checksum field to the end of
    a transmit frame.
    0
    0x0
    RW
    TXE Transmit Enable
    When this bit is set, the transmit module is enabled and placed in a running state. When
    reset, the transmit process is placed in the stopped state after the transmission of the
    current frame is completed.
    Bank 16 Transmit Status Register (0x02): TXSR
    This register keeps the status of the last transmitted frame.
    Bit
    Default Value
    R/W
    Description
    15-6
    0x000
    RO
    Reserved
    5-0
    -
    RO
    TXFID Transmit Frame ID
    This field identifies the transmitted frame. All of the transmit status information in this
    register belongs to the frame with this ID.
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