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參數(shù)資料
型號(hào): PIC16LC72-04/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 90/111頁(yè)
文件大?。?/td> 0K
描述: IC MCU OTP 2KX14 A/D PWM 28SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 47
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
PIC16C72 Series
DS39016A-page 8
Preliminary
1998 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h
Unimplemented
89h
Unimplemented
8Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
ADIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
8Dh
Unimplemented
8Eh
PCON
POR
BOR
---- --qq
---- --uu
8Fh
Unimplemented
90h
Unimplemented
91h
Unimplemented
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP(5)
CKE(5)
D/A
P
S
R/W
UA
BF
0000 0000
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
98h
Unimplemented
99h
Unimplemented
9Ah
Unimplemented
9Bh
Unimplemented
9Ch
Unimplemented
9Dh
Unimplemented
9Eh
Unimplemented
9Fh
ADCON1
PCFG2
PCFG1
PCFG0
---- -000
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5:
SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
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