參數(shù)資料
型號: PIC16LF1503-E/MG
廠商: Microchip Technology
文件頁數(shù): 18/46頁
文件大小: 0K
描述: IC MCU 8BIT 3.5KB FLASH 16QFN
標(biāo)準包裝: 120
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 11
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 16-VFQFN 裸露焊盤
包裝: 管件
26
6222GS–ATARM–6-Sep-11
SAM7SE512/256/32 Summary
The security bit can only be enabled through the Command “Set Security Bit” of the EFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and
after a full flash erase is performed. When the security bit is deactivated, all accesses to the
flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
8.1.2.5
Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD),
so that even after a power loss, the brownout detector operations remain in their state.
These two GPNVM bits can be cleared or set respectively through the commands “Clear Gen-
eral-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.
GPNVM bit 0 is used as a brownout detector enable bit. Setting the GPNVM bit 0 enables the
BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM bit 0 and thus
disables the brownout detector by default.
GPNVM bit 1 is used as a brownout reset enable signal for the reset controller. Setting the
GPNVM bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM
bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.
8.1.2.6
Calibration Bits
Sixteen NVM bits are used to calibrate the brownout detector and the voltage regulator. These
bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on
the calibration bits.
8.1.3
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low.
The Flash of the SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It reads
as 131,072 32-bit words.
The Flash of the SAM7SE256 is organized in 1024 pages of 256 bytes (single plane). It reads
as 65,536 32-bit words.
The Flash of the SAM7SE32 is organized in 256 pages of 128 bytes (single plane). It reads
as 32,768 32-bit words.
The Flash of the SAM7SE512/256 contains a 256-byte write buffer, accessible through a 32-
bit interface.
The Flash of the SAM7SE32 contains a 128-byte write buffer, accessible through a 32-bit
interface.
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