參數(shù)資料
型號(hào): PIC16LF1509T-I/SO
廠商: Microchip Technology
文件頁數(shù): 114/123頁
文件大小: 0K
描述: IC MCU 8BIT 14KB FLASH 20-SOIC
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® XLP™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b,D/A 1x5b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8873MLLJ
September 2011
90
M9999-091911-1.8
Bit
Name
R/W
Description
Default
30-16
Reserved
N/A
Reserved
N/A
15-0
Counter Value
RO
Counter Value
0
Table 16. Format of “All Port Dropped Packet” MIB Counters
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in the following table:
Offset
Counter Name
Description
0x100
Port1 TX Drop Packets
TX packets dropped due to lack of resources
0x101
Port2 TX Drop Packets
TX packets dropped due to lack of resources
0x102
Port3 TX Drop Packets
TX packets dropped due to lack of resources
0x103
Port1 RX Drop Packets
RX packets dropped due to lack of resources
0x104
Port2 RX Drop Packets
RX packets dropped due to lack of resources
0x105
Port3 RX Drop Packets
RX packets dropped due to lack of resources
Table 17. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counters selected
Write to reg. 122 (0x7A) with 0x0e
// Trigger the read operation
Then
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c
// Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e
// Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31]
// If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Write to reg. 121 (0x79) with 0x1d
// Read MIB counter selected
Write to reg. 122 (0x7A) with 0x00
// Trigger the read operation
Then
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
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