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    參數(shù)資料
    型號(hào)： PIC16LF1827-E/MV
    廠商： Microchip Technology
    文件頁(yè)數(shù)： 76/109頁(yè)
    文件大?。?/td> 0K
    描述： MCU 8BIT 4K FLASH 28UQFN
    標(biāo)準(zhǔn)包裝： 91
    系列： PIC® XLP™ mTouch™ 16F
    核心處理器： PIC
    芯體尺寸： 8-位
    速度： 32MHz
    連通性： I²C，SPI，UART/USART
    外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
    輸入/輸出數(shù)： 16
    程序存儲(chǔ)器容量： 7KB（4K x 14）
    程序存儲(chǔ)器類型： 閃存
    EEPROM 大小： 256 x 8
    RAM 容量： 384 x 8
    電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
    振蕩器型： 內(nèi)部
    工作溫度： -40°C ~ 125°C
    封裝/外殼： 28-UFQFN 裸露焊盤(pán)
    包裝： 托盤(pán)
    SC16C850
    All information provided in this document is subject to legal disclaimers.
    NXP B.V. 2010. All rights reserved.
    Product data sheet
    Rev. 2 — 11 November 2010
    29 of 55
    NXP Semiconductors
    SC16C850
    2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
    7.7 Line Status Register (LSR)
    This register provides the status of data transfers between the SC16C850 and the CPU.
    Table 20.
    Line Status Register bits description
    Bit
    Symbol
    Description
    7
    LSR[7]
    FIFO data error.
    logic 0 = no error (normal default condition)
    logic 1 = at least one parity error, framing error or break indication is in the
    current FIFO data. This bit is cleared when there are no remaining error flags
    associated with the remaining data in the FIFO.
    6
    LSR[6]
    THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
    logic 1 whenever the transmit holding register and the transmit shift register are
    both empty. It is reset to logic 0 whenever either the THR or TSR contains a data
    character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and
    transmit shift register are both empty.
    5
    LSR[5]
    THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
    indicates that the UART is ready to accept a new character for transmission. In
    addition, this bit causes the UART to issue an interrupt to CPU when the THR
    interrupt enable is set. The THR bit is set to a logic 1 when a character is
    transferred from the transmit holding register into the transmitter shift register.
    The bit is reset to a logic 0 concurrently with the loading of the transmitter
    holding register by the CPU. In the FIFO mode, this bit is set when the transmit
    FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
    4
    LSR[4]
    Break interrupt.
    logic 0 = no break condition (normal default condition)
    logic 1 = the receiver received a break signal (RX was a logic 0 for one
    character frame time). In the FIFO mode, only one break character is loaded
    into the FIFO.
    3
    LSR[3]
    Framing error.
    logic 0 = no framing error (normal default condition)
    logic 1 = framing error. The receive character did not have a valid stop bit(s).
    In the FIFO mode, this error is associated with the character at the top of the
    FIFO.
    2LSR[2]
    Parity error.
    logic 0 = no parity error (normal default condition)
    logic 1 = parity error. The receive character does not have correct parity
    information and is suspect. In the FIFO mode, this error is associated with the
    character at the top of the FIFO.
    1
    LSR[1]
    Overrun error.
    logic 0 = no overrun error (normal default condition)
    logic 1 = overrun error. A data overrun error occurred in the Receive Shift
    Register. This happens when additional data arrives while the FIFO is full. In
    this case, the previous data in the shift register is overwritten. Note that under
    this condition, the data byte in the Receive Shift Register is not transferred into
    the FIFO, therefore the data in the FIFO is not corrupted by the error.
    0
    LSR[0]
    Receive data ready.
    logic 0 = no data in Receive Holding Register or FIFO (normal default
    condition)
    logic 1 = data has been received and is saved in the Receive Holding Register
    or FIFO
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    參數(shù)描述
    PIC16LF1827-I/ML 功能描述:8位微控制器 -MCU 7KB Flash 384 byte 32 MHz Int. Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    PIC16LF1827-I/MQ 功能描述:8位微控制器 -MCU 7KB Flash 384 byte 32 MHz Int. Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    PIC16LF1827-I/MV 功能描述:8位微控制器 -MCU 7KB Flash 384B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    PIC16LF1827-I/P 功能描述:8位微控制器 -MCU 7KB Flash 384 byte 32 MHz Int. Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
    PIC16LF1827-I/SO 功能描述:8位微控制器 -MCU 7KB Flash 384 byte 32 MHz Int. Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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