參數(shù)資料
型號(hào): PIC16LF1937T-I/MV
廠商: Microchip Technology
文件頁(yè)數(shù): 10/14頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 512KX14 40UQFN
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® XLP™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-UFQFN 裸露焊盤(pán)
包裝: 帶卷 (TR)
2009-2012 Microchip Technology Inc.
DS80479K-page 5
PIC16(L)F1934/1936/1937
5.
Module: ADC
5.1 Analog-to-Digital Conversion
An ADC conversion may not complete under these
conditions:
1.
When FOSC is greater than 8 MHz and it is the
clock source used for the ADC converter.
2.
The ADC is operating from its dedicated internal
FRC oscillator and the device is not in Sleep
mode (any FOSC frequency).
When this occurs, the ADC Interrupt Flag (ADIF)
does not get set, the GO/DONE bit does not get
cleared, and the conversion result does not get
loaded into the ADRESH and ADRESL result
registers.
Work around
Method 1: Select the system clock, FOSC, as
the ADC clock source and reduce
the FOSC frequency to 8 MHz or
less
when
performing
ADC
conversions.
Method 2: Select
the
dedicated
FRC
oscillator as the ADC conversion
clock source and perform all
conversions with the device in
Sleep.
Method 3: This method is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above 8
MHz. This method requires early
termination of an ADC conver-
sion. Provide a fixed time delay in
software
to
stop
the
A-to-D
conversion manually, after all 10
bits are converted, but before the
conversion
would
complete
automatically. The conversion is
stopped by clearing the GO/
DONE bit in software. The GO/
DONE bit must be cleared during
the last TAD cycle, before the
conversion
would
have
completed automatically. Refer to
Figure 1 for details.
FIGURE 1:
INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full conversion. Each TAD
cycle consists of 8 TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 sec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD
11 TAD
Stop the A/D conversion
between 10.5 and 11 TAD
cycles.
See the Analog-to-Digital
Conversion Timing diagram
in
the
Analog-to-Digital
Converter chapter of the
device data sheet.
}
See the ADC Clock Period (TAD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
chapter of the device data sheet.
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