參數(shù)資料
型號: PIC16LF627-04/P
廠商: Microchip Technology
文件頁數(shù): 131/170頁
文件大小: 0K
描述: IC MCU FLASH 1KX14 COMP 18DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: PIC16LF627-04/PR
PIC16LF627-04/PR-ND
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 61
PIC16F62X
11.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 11-1 shows the
timer resources of the CCP Module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro Mid-Range Reference Manual,
(DS33023).
TABLE 11-1:
CCP MODE - TIMER
RESOURCE
REGISTER 11-1:
CCP1CON REGISTER (ADDRESS: 17h)
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer2
U-0
R/W-0
CCP1X
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
bit 3-0
CCP1M3:CCP1M0: CCPx Mode Select bits
0000
= Capture/Compare/PWM off (resets CCP1 module)
0100
= Capture mode, every falling edge
0101
= Capture mode, every rising edge
0110
= Capture mode, every 4th rising edge
0111
= Capture mode, every 16th rising edge
1000
= Compare mode, set output on match (CCP1IF bit is set)
1001
= Compare mode, clear output on match (CCP1IF bit is set)
1010
= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011
= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx
= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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