參數(shù)資料
型號(hào): PIC16LF74-I/L
廠商: Microchip Technology
文件頁數(shù): 54/104頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX14 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 640 (CN2011-ZH PDF)
其它名稱: PIC16LF74I/L
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
45
M9999-030210-1.0
Register Map: MAC, PHY and QMU
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to Clear (writing an “1” to clear this bit).
0x00 – 0x07: Reserved
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options.
Bit
Default Value
R/W
Description
15-11
-
RO
Reserved.
10
-
RO
Bus Endian mode
The EESK (pin 10) value is latched into this bit druing power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
9
-
RO
EEPROM presence
The EED_IO (pin 9) value is latched into this bit druing power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
8
0
RO
Reserved.
7
-
RO
8-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
6
-
RO
16-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 16-bit bus mode operation, 1: In 16-bit bus mode operation.
5
0
RO
Reserved.
4
-
RO
Shared data bus mode for data and address
0: Data and address bus are seperated.
1: Data and address bus are shared.
3
0
RO
Reserved.
2
0
RO
Reserved.
1
-
RO
48-Pin Chip Package
To indicate chip package is 48-pin.
0: No, 1: Yes.
0
RO
Reserved.
0x0A – 0x0F: Reserved
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